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19-1996; Rev 1; 12/01
KIT ATION EVALU BLE AVAILA
+3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with Clock Recovery
General Description Features
o Single +3.3V Supply o 530mW Operating Power o Fully Integrated Clock Recovery and Data Retiming o Exceeds ANSI, ITU, and Bellcore Specifications o Additional High-Speed Input Facilitates System Loopback Diagnostic Testing o 2.488Gbps Serial to 155Mbps Parallel Conversion o Differential PECL Clock Output o Single-Ended PECL Data Outputs o Tolerates >2000 Consecutive Identical Digits o Loss-of-Lock Indicator
MAX3881
The MAX3881 deserializer with clock recovery is ideal for converting 2.488Gbps serial data to 16-bit-wide, 155Mbps parallel data for SDH/SONET applications. Operating from a single +3.3V supply, this device accepts high-speed serial-data inputs and delivers single-ended PECL parallel data outputs and a differential PECL parallel clock output for interfacing with digital circuitry. The MAX3881 includes a low-power clock recovery and data retiming function for 2.488Gbps applications. The fully integrated phase-locked loop (PLL) recovers a synchronous clock signal from the serial NRZ data input; the signal is then retimed by the recovered clock. The MAX3881's jitter performance exceeds all SDH/SONET specifications. An additional 2.488Gbps serial input is available for system loopback diagnostic testing. The device also includes a TTL-compatible loss-of-lock (LOL) monitor. The MAX3881 is available in the extended temperature range (-40C to +85C) in a 64-pin TQFP-EP package.
Ordering Information
PART MAX3881ECB *Exposed pad TEMP. RANGE -40C to +85C PIN-PACKAGE 64 TQFP-EP*
Applications
PD15 PD14 GND GND LOL VCC VCC
Pin Configuration
TOP VIEW
PD13 PD12 PD11 GND GND VCC VCC VCC VCC
2.488Gbps SDH/SONET Transmission Systems Add/Drop Multiplexers Digital Cross-Connects
64
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
GND FIL+ FILVCC PHADJ+ PHADJVCC SDI+ SDIVCC SLBI+ SLBIVCC SIS GND GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
48 47 46 45 44 43 42 41
VCC PD10 VCC PD9 VCC PD8 VCC GND VCC PD7 VCC PD6 VCC PD5 VCC GND
Typical Application Circuit appears at end of data sheet.
MAX3881
40 39 38 37 36 35 34 33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PD1
PD2
PD4
VCC
VCC
VCC
PCLK+
PCLK-
GND
PD0
GND
TQFP-EP*
*EXPOSED PAD IS CONNECTED TO GND.
________________________________________________________________ Maxim Integrated Products
PD3
VCC
VCC
VCC
VCC
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
+3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with Clock Recovery MAX3881
ABSOLUTE MAXIMUM RATINGS
Positive Supply Voltage (VCC)...............................-0.5V to +7.0V Input Voltage Level (SDI+, SDI-, SLBI+, SLBI-) ...............................(VCC - 0.5V) to (VCC + 0.5V) Input Current Level (SDI+, SDI-, SLBI+, SLBI-)................10mA Voltage at LOL, SIS, PHADJ+, PHADJ-, FIL+, FIL- .................................................-0.5V to (VCC + 0.5V) PECL Output Current ..........................................................50mA Continuous Power Dissipation (TA = +85C) 64-Pin TQFP (derate 33.3mW/C above +85C)............1.44W Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-55C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, PECL loads = 50 to (VCC - 2V), TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25C.) PARAMETER Supply Current Differential Input Voltage Single-Ended Input Voltage Input Termination to VCC PECL OUTPUTS (PD_, PCLK) TA = 0C to +85C PECL Output High Voltage VOH TA = -40C to 0C TA = 0C to +85C PECL Output Low Voltage VOL TA = -40C to 0C TTL INPUTS AND OUTPUTS (SIS, LOL) Input High Voltage Input Low Voltage Input Current Output High Voltage Output Low Voltage VOH VOL IOH 40A IOL 1mA VIH VIL -10 2.4 2.0 0.8 +10 VCC 0.4 V V A V V VCC 1.025 VCC 1.085 VCC 1.81 VCC 1.83 VCC 0.88 VCC 0.88 VCC 1.62 VCC 1.555 SYMBOL ICC VID VIS RIN Figure 2 CONDITIONS Excluding PECL outputs Figure 1 50 VCC - 0.4 50 MIN TYP 160 MAX 240 800 VCC + 0.2 UNITS mA mVp-p V
SERIAL DATA INPUTS (SDI, SLBI)
V
V
2
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+3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with Clock Recovery
AC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, PECL loads = 50 to (VCC - 2V), TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25C.) (Note 1) PARAMETER Serial Data Rate Parallel Output Data Rate Parallel Clock-to-Data Output Delay tCLK-Q Figure 2 f = 70kHz (Note 2) Jitter Tolerance f = 100kHz f = 1MHz f = 10MHz Tolerated Consecutive Identical Digits Input Return Loss (SDI, SLBI) Output Edge Speed 100kHz to 2.5GHz 2.5GHz to 4.0GHz 200 2.31 1.74 0.38 0.28 SYMBOL SDI CONDITIONS MIN TYP 2.488 155.52 450 3.3 2.41 0.57 0.46 >2,000 -18 -11 800 Bits dB ps UIp-p 900 MAX UNITS Gbps Mbps ps
MAX3881
tR, tF
20% to 80%
Note 1: AC characteristics are guaranteed by design and characterization. Note 2: At jitter frequencies <70kHz, the jitter tolerance of the MAX3881 outperforms the ITU/Bellcore specifications.
SDI+ SDI-
25mV MIN 400mV MAX
PCLK tCLK-Q
(SDI+) - (SDI-)
VID
50mVp-p MIN 800mVp-p MAX
PD0-PD15
Figure 1. Input Amplitude
Figure 2. Timing Parameters
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+3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with Clock Recovery MAX3881
Typical Operating Characteristics
(VCC = +3.3V, TA = +25C, unless otherwise noted.)
RECOVERED DATA AND CLOCK
MAX3881-01
SUPPLY CURRENT vs. TEMPERATURE
MAX3881-02
JITTER TOLERANCE
CF = 0.1F INPUT JITTER (UIp-p) CF = 1.0F
MAX3881 toc03
200 190 SUPPLY CURRENT (mA) 180 170 160 VCC = +3.0V 150 140
10.0
DATA
223 - 1 PATTERN
1.0
VCC = +3.6V
CLOCK
0.1 -50 -25 0 25 50 75 100 10 TEMPERATURE (C) 1,000 100 JITTER FREQUENCY (kHz) 10,000
1.64ns/div
JITTER TOLERANCE vs. INPUT VOLTAGE
0.9
MAX3881 toc04
BIT ERROR RATIO vs. INPUT VOLTAGE
MAX3881-05
PARALLEL CLOCK TO DATA OUTPUT PROPAGATION DELAY vs. TEMPERATURE
PCLK TO DATA OUTPUT PROPAGATION DELAY (ps)
MAX3881-06
1 JITTER FREQUENCY = 1MHz
10-3 10-4 BIT ERROR RATIO 10-5 10-6 10-7 10-8 10-9 10-10
700
JITTER TOLERNCE (UIp-p)
0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 10
600
JITTER FREQUENCY = 5MHz
500
400
SONET SPEC
300
200 -50 -25 0 25 50 75 100 TEMPERATURE (C)
100 INPUT VOLTAGE (mVp-p)
1000
8.0
8.5
9.0
9.5
10
INPUT VOLTAGE (mVp-p)
4
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+3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with Clock Recovery
Pin Description
PIN 1, 15, 16, 17, 25, 33, 41, 49, 57, 62, 64 2 3 4, 7, 10, 13, 20, 22, 24, 26, 28, 30, 32, 34, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60 5 6 8 9 11 12 14 18 19 21, 23, 27, 29, 31, 35, 37, 39, 43, 45, 47, 51, 53, 55, 59, 61 63 EP NAME FUNCTION
MAX3881
GND
Ground
FIL+ FIL-
Positive Filter Input. PLL loop filter connection. Connect a 1.0F capacitor between FIL+ and FIL-. Negative Filter Input. PLL loop filter connection. Connect a 1.0F capacitor between FIL+ and FIL-.
VCC
+3.3V Supply Voltage
PHADJ+ PHADJSDI+ SDISLBI+ SLBISIS PCLK+ PCLK-
Positive Phase-Adjust Input. Used to optimally align internal PLL phase. Connect to VCC if not used. Negative Phase-Adjust Input. Used to optimally align internal PLL phase. Connect to VCC if not used. Positive Serial Data Input. 2.488Gbps data stream. Negative Serial Data Input. 2.488Gbps data stream. Positive System Loopback Input. 2.488Gbps data stream. Negative System Loopback Input. 2.488Gbps data stream. Signal Input Selection. TTL low for normal data input (SDI). TTL high for system loopback input (SLBI). Positive Parallel Clock PECL Output Negative Parallel Clock PECL Output
PD0 to PD15
Parallel Data Single-Ended PECL Outputs. Data is updated on the negative transition of the PCLK signal (Figure 2).
LOL Exposed Pad
Loss-of-Lock Output. PLL loss-of-lock monitor, TTL active low (internal 10k pullup resistor). The LOL monitor is valid only when a data stream is present on the inputs to the MAX3881. Ground. This must be soldered to a circuit board for proper electrical and thermal performance (see Package Information).
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5
+3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with Clock Recovery MAX3881
PHADJ+ VCC PHADJFIL+ FIL-
50 SDI+ AMP SDI0 MUX SLBI+ 0 AMP SLBII 50 PECL VCC SIS PD0 I PHASE & FREQUENCY DETECTOR LOOP FILTER VCO 16-BIT DEMULTIPLEXER D CK Q PECL PD15
PECL
PD1
MAX3881
CLOCK DIVIDER PECL
PCLK+ PCLK-
TTL
LOL
Figure 3. MAX3881 Functional Diagram
Detailed Description
The MAX3881 deserializer with clock recovery converts 2.488Gbps serial data to 16-bit-wide, 155Mbps parallel data. The device combines a fully integrated phaselocked loop (PLL), input amplifier, data retiming block, 16-bit demultiplexer, clock divider, and PECL output buffer (Figure 3). The PLL consists of a phase/frequency detector (PFD), a loop filter, and a voltage-controlled oscillator (VCO). The MAX3881 is designed to deliver the best combination of jitter performance and power
dissipation by using a differential signal architecture and low-noise design techniques. The PLL recovers the serial clock from the serial input data stream. The demultiplexer generates a 16-bit-wide 155Mbps parallel data output.
Input Amplifier
The input amplifiers on both the main data and system loopback accept a differential input amplitude from 50mVp-p to 800mVp-p. The bit error ratio (BER) is better than 1 x 10-10 for input signals as small as 9.5mVp-p,
6
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+3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with Clock Recovery
although the jitter tolerance performance will be degraded. For interfacing with PECL signal levels, see Applications Information. Interfacing Between CML, PECL, and LVDS for more details regarding the Thevenin-equivalent PECL termination.
MAX3881
Phase Detector
The phase detector in the MAX3881 produces a voltage proportional to the phase difference between the incoming data and the internal clock. Because of its feedback nature, the PLL drives the error voltage to zero, aligning the recovered clock to the center of the incoming data eye for retiming. The external phase adjust pins (PHADJ+, PHADJ-) allow the user to vary the internal phase alignment.
Design Procedure
Jitter Tolerance and Input Sensitivity Trade-Offs
When the received data amplitude is higher than 50mVp-p, the MAX3881 provides a typical jitter tolerance of 0.46UIp-p at jitter frequencies greater than 10MHz. The SDH/SONET jitter tolerance specification is 0.15UIp-p, leaving a jitter allowance of 0.31UIp-p for receiver preamplifier and postamplifier design. The BER is better than 1 x 10 -10 for input signals greater than 9.5mVp-p. At 25mVp-p, jitter tolerance will be degraded, but will still be above the SDH/SONET requirement. Trade-offs can be made between jitter tolerance and input voltage according to the specific application. See the Typical Operating Characteristics for Jitter Tolerance and BER vs. Input Voltage graphs.
Frequency Detector
The digital frequency detector (FD) aids frequency acquisition during start-up conditions. The frequency difference between the received data and the VCO clock is derived by sampling the in-phase and quadrature VCO outputs on both edges of the data input signal. Depending on the polarity of the frequency difference, the FD drives the VCO until the frequency difference is reduced to zero. Once frequency acquisition is complete, the FD returns to a neutral state. False locking is completely eliminated by this digital frequency detector.
Applications Information
Consecutive Identical Digits (CIDs)
The MAX3881 has a low phase and frequency drift in the absence of data transitions. As a result, long runs of consecutive zeros and ones can be tolerated while maintaining a BER of 1 x 10-10. The CID tolerance is tested using a 2 13 - 1 pseudorandom bit stream (PRBS), substituting a long run of zeros to simulate the worst case. A CID tolerance of greater than 2,000 bits is typical.
Loop Filter and VCO
The phase detector and frequency detector outputs are summed into the loop filter. A 1.0F capacitor, CF, is required to set the PLL damping ratio. The loop filter output controls the on-chip LC VCO running at 2.488GHz. The VCO provides low phase noise and is trimmed to the correct frequency.
Phase Adjust
The internal clock is aligned to the center of the data eye. For specific applications, this sampling position can be shifted using the PHADJ inputs to optimize BER performance. The PHADJ inputs operate with differential input voltages up to 1.5V. A simple resistor-divider with a bypass capacitor is sufficient to set these levels (Figure 4). When the PHADJ inputs are not used, they should be tied directly to VCC.
Loss-of-Lock Monitor
A loss-of-lock (LOL) monitor is included in the MAX3881 frequency detector. A loss-of-lock condition is signaled with a TTL low. When the PLL is frequencylocked, LOL switches to TTL high in approximately 800ns. Note that the LOL monitor is only valid when a data stream is present on the inputs to the MAX3881. As a result, LOL does not detect a loss-of-power condition resulting from a loss of the incoming signal.
System Loopback
The MAX3881 is designed to allow system loopback testing. The user can connect a serializer output (MAX3891) in a transceiver directly to the SLBI+ and SLBI- inputs of the MAX3881 for system diagnostics. To select the SLBI inputs, apply a TTL logic high to the SIS pin.
Positive Emitter-Coupled Logic (PECL) Outputs
The MAX3881 features PECL outputs for the parallel clock and data outputs. For proper operation, PECL outputs should be terminated with 50 to (VCC - 2V). In many cases, it is not feasible to use the 50 to (VCC 2V) termination, so it may be preferable to terminate to the Thevenin equivalent. See application note HFAN-1,
Interfacing with PECL Input Levels
When interfacing with differential PECL input levels, it is important to attenuate the signal while still maintaining
7
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+3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with Clock Recovery MAX3881
50 termination (Figure 5). AC-coupling is also required to maintain the input common-mode level.
VCC
Exposed-Pad Package
The exposed-pad (EP), 64-pin TQFP incorporates features that provide a very low thermal-resistance path for heat removal from the IC. The pad is electrical ground on the MAX3881 and must be soldered to the circuit board for proper thermal and electrical performance.
50 0.1F PECL LEVELS 0.1F SDI25 50
SDI+
100
Layout Techniques
For best performance, use good high-frequency layout techniques. Filter voltage supplies, keep ground connections short, and use multiple vias where possible. Use controlled-impedance transmission lines to interface with the MAX3881 high-speed inputs and outputs. Power-supply decoupling should be placed as close to V CC pins as possible. To reduce feedthrough, take care to isolate the input signals from the output signals.
25
MAX3881
Figure 5. Interfacing with PECL Input Levels
Chip Information
3.3V
MAX3881
PHADJ+ (PIN 5)
TRANSISTOR COUNT: 2231 PROCESS: BiPolar
PHADJ- (PIN 6)
Figure 4. Phase-Adjust Resistor-Divider
8
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+3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with Clock Recovery
Typical Application Circuit
+3.3V 0.01F
MAX3881
PHADJ+
PHADJ-
VCC
+3.3V 124 PD15 84.5 +3.3V 124
VCC
+3.3V VCC FIL IN+ OUT+ SDI+
PD0
MAX3881
84.5
+3.3V 124
MAX3866
PRE/POSTAMPLIFIER OUTLOP SDIPCLK+
OVERHEAD TERMINATION
84.5 SLBISLBI+ +3.3V 124 SIS SYSTEM LOOPBACK FIL+ FILGND LOL PCLK-
TTL
84.5 CF 1.0F TTL TTL EXTERNAL TERMINATION REQUIRED ONLY IF OVERHEAD CIRCUIT DOES NOT INCLUDE INTERNAL INPUT TERMINATION. THIS SYMBOL REPRESENTS A TRANSMISSION LINE OF CHARACTERISTIC IMPEDANCE Z0 = 50.
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9
+3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with Clock Recovery MAX3881
Package Information
64L, TQFP.EPS 10 ______________________________________________________________________________________
+3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with Clock Recovery
Package Information (continued)
MAX3881
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 11 (c) 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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